英语词汇“plesiochronous”的意思、用法、释义、翻译、读音、例句、短语、词组-英语词典

学习怎么用

权威例句

plesiochronous
plesiochronous
Plesiochronous
METHOD FOR MAINTAINING PLESIOCHRONOUS ENTITIES
Low-latency plesiochronous data retiming
5 Gb/s bidirectional balanced-line link compliant with plesiochronous clocking
A 2B parallel 1.25 Gb/s interconnect I/O interface with self-configurable link and plesiochronous clocking
5 Gb/s bidirectional balanced-line link compliant with plesiochronous clocking
A 2-Byte Parallel 1.25 Gb/s Interconnect I/O Interface with Self-Configurable Link and Plesiochronous Clocking
A 285 MHz 6-port plesiochronous router chip with non-blocking cross-bar switch
A 9.6 GigaByte/s throughput plesiochronous routing chip
A 9.6 GigaByte/s Throughput Plesiochronous Routing Chip
Design and implementation of a plesiochronous multi-core 4x4 network-on-chip FPGA platform with MPI HAL support

单词	plesiochronous
释义	plesiochronous 听听怎么读英 [p'li:si:??kr?n?s] 美 [p'lisio?kr?n?s] 是什么意思 adj. 准同步的；学习怎么用权威例句 plesiochronous plesiochronous Plesiochronous METHOD FOR MAINTAINING PLESIOCHRONOUS ENTITIES Low-latency plesiochronous data retiming 5 Gb/s bidirectional balanced-line link compliant with plesiochronous clocking A 2B parallel 1.25 Gb/s interconnect I/O interface with self-configurable link and plesiochronous clocking 5 Gb/s bidirectional balanced-line link compliant with plesiochronous clocking A 2-Byte Parallel 1.25 Gb/s Interconnect I/O Interface with Self-Configurable Link and Plesiochronous Clocking A 285 MHz 6-port plesiochronous router chip with non-blocking cross-bar switch A 9.6 GigaByte/s throughput plesiochronous routing chip A 9.6 GigaByte/s Throughput Plesiochronous Routing Chip Design and implementation of a plesiochronous multi-core 4x4 network-on-chip FPGA platform with MPI HAL support
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